Raspberry Pi OLED/LCD HAT (A) User Guide

Introduction

The OLED/LCD HAT (A) features a 2-inch IPS screen with the built-in ST7789VW driver and support using SPI communication. Also, it boasts a wide viewing angle and supports a 262K color display with 240x320 resolution. Dual 0.96-inch OLED screen with a built-in driver, support using I2C communication, and blue display with 128x64 resolution for displaying key information, status indicator, or mini graphics. In addition, we provide demos for Raspberry Pi (BCM2835 library, WiringPi library, and Python demo), STM32, and Arduino.

Parameters

Pins

Hardware Description

LCD & Drivers

The LCD supports 12-bit, 16-bit, and 18-bit input color formats for each pixel, that is, RGB444, RGB565, and RGB666. The demo we used here is the RGB565 color format, which is commonly used.
For most LCD drivers, the communication methods for controlling the drive are supported such as the 8080 parallel interface, 3-wire SPI, and 4-wire SPI. This LCD adopts a 4-wire SPI communication interface, which can significantly reduce the usage of GPIO headers and improve communication rate.

Communication Protocol

From the above, we know that 4-wire SPI communication is used, and we can get the following communication timing diagram by checking the datasheet to transmit RGB556 as an example:
Note: Different from the traditional SPI protocol, the data line from the slave to the master is hidden since the device only has a display requirement.
RESX Is the reset pin, it should be low when powering the module and be higher at other times.
CSX is slave chip select, when CS is low, the chip is enabled.
D/CX is data/command control pin, when DC = 0, write command, when DC = 1, write data
SDA is the data pin for transmitting RGB data, it works as the MOSI pin of the SPI interface;
SCL works the SCLK pins of the SPI interface.
SPI communication has data transfer timing, which is combined by CPHA and CPOL.
The high or low CPHA determines whether the serial synchronization clock is used for data acquisition at the first or second clock tick edge; when CPHA = 0, data acquisition is performed at the first tick edge.
CPOL determines the level of the serial synchronous clock at an idle state. When CPOL = 0, the level is Low. However, CPOL has little effect on the transmission.
CPHA determines whether data is collected at the first clock edge or at the second clock edge of the serial synchronous clock; when CPHL = 0, data is collected at the first clock edge.
As can be seen from the figure, when the first falling edge of SCLK starts transmitting data, a clock cycle to transmit 8-bit data, the use of SPI0, bit-by-bit transmission, the high bit in the front, the low bit in the back.

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